IBM's new sub-1 nm uses Nanostack Architecture against traditional 2nm chips.
NEW YORK: On June 25 2026, IBM announced what it describes as the world’s first sub-1 nanometer chip technology from its research headquarters in Yorktown Heights, New York. The chip operates at 0.7 nanometres also described as 7 angstroms, a unit used to measure individual atoms and packs nearly 100 billion transistors onto a piece of silicon the size of a fingernail. That is approximately twice the density of IBM’s 2nm chip announced in 2021, which was itself the smallest node in the world at the time. Jay Gambetta, Director of IBM Research, said: “With our new nanostack architecture, we’re not just making smaller transistors, we’re reinventing how chips are built to deliver dramatically more power and energy efficiency.”
IBM claims the new technology delivers up to 50 percent more computing performance at equivalent power or alternatively up to 70 percent lower energy consumption compared to its 2nm baseline.
Why Going Smaller Stopped Working
To understand what IBM has done, the problem it was solving needs to be clear first. A nanometre is one-billionth of a metre roughly the width of a few atoms. The current industry standard sits around 2 to 3nm. At that scale transistors are already so small that electrons begin leaking across barriers they are supposed to stay behind, a quantum mechanical problem that cannot be engineered away by simply shrinking further.
For decades chipmakers solved this with the nanosheet transistor, also invented by IBM where multiple thin horizontal silicon sheets are wrapped by a gate on all sides, improving control over electron flow. However even nanosheet technology has hit physical limits. Making transistors smaller across a flat surface is running out of room.
IBM’s answer is to stop going sideways and start going up. The nanostack architecture stacks complementary transistor types ‘n-type’ and ‘p-type’ in vertical layers rather than placing them side by side on the same plane. Professor Alan Woodward of Surrey University described the ambition to the BBC this way: if existing 3D chip efforts from Samsung and Intel are the equivalent of 30 to 50-storey buildings, IBM’s nanostack is a 100-storey skyscraper.
How IBM Proved It Works
Building a chip at atomic scale requires proving the structure can be physically constructed and actually perform computation. IBM confirmed three specific laboratory validations. First, ultra-thin dielectric wafer bonding joining two separately fabricated wafers, one carrying n-type transistors and one carrying p-type both with atomic-level precision. Second, dual-channel engineering because the layers are processed separately before bonding, each can be optimised independently using different materials, silicon for one layer and silicon-germanium for the other, maximising electron flow in both. Third, a functional CMOS inverter, the most basic building block of digital logic, which switches a 1 to a 0. A working inverter demonstrates the stacked transistors can communicate and perform real binary computation.
The architecture was first detailed in a peer-reviewed paper by S. Reboh et al. at the VLSI 2025 symposium. A second paper by Chen Zhang et al. at VLSI 2026 demonstrated a 40 percent reduction in SRAM cell height using nanostack a significant result because AI workloads are heavily memory-dependent and SRAM scaling had been largely stalled for a decade.
Lam Research, Tokyo Electron and SCREEN Semiconductor Solutions are collaborating with IBM on the process development needed to translate this laboratory work into manufacturable technology. Their involvement matters because converting a research prototype into a production-ready process requires specialised equipment operating at atomic precision across millions of chips.
The Engineering Challenges That Remain
The primary problem with stacking transistors vertically is heat. Transistors generate heat when they switch, and in a vertical stack that heat has nowhere easy to go. The upper layer acts as an insulator for the lower one. IBM intends to address this through advanced thermal interface materials and backside power delivery systems that free up routing space for direct thermal channels but this remains an engineering challenge that must be solved at scale.
Achieving defect-free wafer bonding at production volumes is a second major barrier. Nanoscale misalignment between the two bonded wafers or any contamination at the bonding interface, destroys the electrical contacts between layers. IBM’s production viability estimate of five years placing potential commercial availability around 2031.
IBM’s own history with its 2nm chip announced in 2021, provides the relevant precedent. That chip is only now approaching volume production five years later. IBM does not manufacture commercial logic chips at volume itself. It licenses architectural innovations to foundries including TSMC, Samsung, Intel and Japan’s state-backed Rapidus, which is already building a 2nm fabrication facility in Hokkaido using IBM-derived technology and is a natural candidate for future nanostack commercialisation.
What It Means for AI Hardware
The SRAM scaling result presented at VLSI 2026 carries direct implications for AI infrastructure. Systems designed for large language model inference rely heavily on on-chip SRAM to store model weights and avoid repeated access to slower external memory. A 40 percent reduction in SRAM cell height means significantly more memory can be integrated onto the same die, which could reduce the latency and energy cost of running frontier AI models. Industry analysts at TechInsights described the announcement as transformational precisely because it restarts SRAM scaling at the moment AI hardware has become most memory-constrained.
Where India Stands
IBM has active agreements with Indian entities including a 2023 MoU with MeitY to act as a knowledge partner for the India Semiconductor Mission, a 2024 MoU with C-DAC on processor design using IBM Power architecture and a 2024 agreement with L&T Semiconductor Technologies for co-designing industrial processors.
India’s own frontier chip effort is C-DAC’s AUM processor, built on TSMC’s 5nm technology a significant distance from the 0.7nm node IBM has demonstrated. India’s semiconductor imports stand at USD 30 to 35 billion annually, a dependency concentrated in advanced logic chips, silicon wafers and packaging materials.
Whether IBM’s nanostack eventually reaches commercial production on schedule is a question the semiconductor industry will be watching closely and one that the five-year history of the 2nm chip suggests should be held with appropriate patience.
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